Sr. Design Engineer
Ursus
2 days ago
Contract
Remote
United States
$102 - $112.50 USD hourly
JOB TITLE: Sr. Design Engineer
LOCATION: Remote
DURATION: Through 06/30/2027
PAY RANGE: $102 - $112/hr.
RESPONSIBILITIES:
QUALIFICATIONS:
PREFERRED QUALIFICATIONS:
EDUCATION:
BENEFITS SUMMARY: Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full-time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
IND123
BENEFITS SUMMARY:
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full-time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
FAIR CHANCE POLICY:
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
LOCATION: Remote
DURATION: Through 06/30/2027
PAY RANGE: $102 - $112/hr.
RESPONSIBILITIES:
- Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs.
- Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
- Develop verification methodologies and test benches for block- and system-level verification
- Create and execute test plans, develop test harnesses, and implement coverage models
- Conduct timing analysis, noise analysis, and other sign-off checks
- Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
- Support lab integration and troubleshooting activities
- Resolve design issues and drive solutions for timing, congestion, and other implementation challenges
QUALIFICATIONS:
- 7+ years of experience in ASIC design and implementation
- Bachelor's degree in Electrical Engineering,
- Computer Engineering, or related technical discipline.
- Experience with FPGA & ASIC design. Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
- Experience with Linux development environment
- Experience with design verification and test bench development
PREFERRED QUALIFICATIONS:
- Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
- Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
- Experience with Software-Defined Radio Architectures, Client/DAC, and/or DSPs
- Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM).
- Strong object-oriented programming and scripting skills (Python, TCL, Perl)
- Experience with physical design flows and industry-standard EDA tools
- Experience with RTL2GDSII physical design and signoff flows.
- Knowledge of deep sub-micron FinFET and CMOS technologies.
- Experience with DFT/Scan/MBIST/LBIST methodologies.
- Experience mentoring junior engineers
EDUCATION:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
- Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
BENEFITS SUMMARY: Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full-time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
IND123
BENEFITS SUMMARY:
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full-time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
FAIR CHANCE POLICY:
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.